1. Field of the Invention
The present invention relates to a method for dealing with errors in a computer system, and more particularly relates to a method for dealing with errors used in a multiplexed computer system.
2. Description of the Related Art
It is known that there is a computer system having a high reliability such as a fault tolerant computer system. In the fault tolerant computer system, all of hardware modules constituting the system are duplicated or multiplexed. All of the hardware modules are synchronously operated. For this reason, for example, even if a certain portion of the system is troubled, the hardware module with the trouble can be separated, thereby continuing the process under the normal hardware modules. Thus, the tolerance for the trouble is improved.
Errors occurring in the computer system have various levels of influences on the system. If the same method is used to deal with all the errors, the method for dealing with the errors having the high influence level must be used. In this case, the method unnecessarily thoroughly deals with the error, even though the error has the low influence level. This makes the burden on the system unnecessarily large, which leads to the possibility that the processing performance is excessively influenced. Thus, a technique is desired, which can deal with the error correspondingly to the influence level on the system.
In conjunction with the above description, Japanese Laid-Open Patent Application (JP-A-Heisei, 7-200334) discloses a dually synchronous driving method. In this dually synchronous driving method, two processor groups, which are substantially equal to each other, are driven synchronously with each other by the same command and the same data input. One of the two processor groups is assigned to an active group, and the other is assigned to a standby group. A trouble detecting circuit for detecting a hardware trouble is connected to each of the two processor groups. Here, if the hardware trouble occurs in a processor group, an operation cannot be normally continued in the processor group. Each of the two processors contains a first controller and a second controller. The first controller belonging to the active group executes an interrupting process based on a detection output from the trouble detecting circuit of the active group, releases the synchronous state, and then stops displaying the active group. The second controller belonging to the standby group starts displaying the active group based on the detection output from the trouble detecting circuit of a partner's group, and then continues the operation at a single mode.